Catch up on the essentials
- Seoul Economic Daily, citing analysts, noted that the 11.95-nanometer figure measures a specific core structure and is therefore difficult to compare directly with the "12-nanometer-class" process names used by Samsung, SK hynix and Micron.
- CXMT used the platform launch to unveil two 24-gigabit LPDDR5X products, a power-saving DRAM class used mainly in smartphones and other portable electronics.
- CXMT said it developed the platform using computer simulations and joint work with Chinese chip-equipment makers on critical production steps, a detail that aligns with Beijing's drive to reduce reliance on foreign semiconductor technology.
Selected from this article · 2026-09-21
Read on for the full pictureCXMT's G5 platform and the 11.95-nanometer claim

Chinese DRAM maker CXMT said on September 20, 2026 that its fifth-generation technology platform, known as G5, has entered mass production, a step the company framed as a competitive challenge to Samsung Electronics, SK Hynix and Micron Technology in the global memory market. CXMT, China's leading DRAM producer and now listed on Shanghai's STAR Market, said the platform uses 11.95-nanometer spacing for key features in the data-storage portion of the chip, achieved through a "quadruple patterning" process that repeats manufacturing steps to produce finer circuit patterns. Vice president and marketing-center chief Luo Xiaodong, speaking at the 2026 World Manufacturing Convention in Hefei, said "Our process capability is now on par with the most advanced mass-produced nodes out there in the industry." Seoul Economic Daily, citing analysts, noted that the 11.95-nanometer figure measures a specific core structure and is therefore difficult to compare directly with the "12-nanometer-class" process names used by Samsung, SK hynix and Micron.
Density gains and the 24Gb LPDDR5X products
CXMT used the platform launch to unveil two 24-gigabit LPDDR5X products, a power-saving DRAM class used mainly in smartphones and other portable electronics. Each die holds 50 percent more data than CXMT's previous equivalent products, and both are already in volume production, the company said, offered in two package formats for different device designs. On a per-wafer basis, CXMT said the platform can yield at least 50 percent more gross chip dies than its fourth-generation platform using an 8Gb baseline. The figure counts potential chips before defective units are screened out, rather than the share that pass final testing, and CXMT did not disclose specific yields or monthly output figures.
Domestic tool chain and the export-control backdrop
CXMT said it developed the platform using computer simulations and joint work with Chinese chip-equipment makers on critical production steps, a detail that aligns with Beijing's drive to reduce reliance on foreign semiconductor technology. The announcement comes against the backdrop of U.S. export controls in place since 2022 that have restricted China's access to certain advanced chipmaking equipment and related software. Reporting also noted that CXMT, headquartered in Hefei in Anhui province, unveiled the platform at a manufacturing convention in its home city, framing the event as both a technology milestone and a domestic-supply statement.
What remains undisclosed and what comes next
CXMT did not disclose specific yield rates or monthly wafer output for the G5 platform, leaving a gap between the claimed die-density improvement and the actual shipment capacity the new line can support. Independent benchmarking against Samsung, SK Hynix and Micron on shipped product — rather than gross die counts — is also not yet available. Market attention now turns to how quickly CXMT converts the platform into commercial shipments for smartphone and PC customers, and whether subsequent disclosures narrow the reported gap with the established DRAM leaders.
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